The present invention relates to a display memory control system and, more particularly, to a display memory control system of the type wherein video data are developed in a display memory on a bit map basis.
In a display system for displaying with the bit map principle such images as characters and graphs on a cathode ray tube (CRT) or like display unit which requires refreshing, pixel data associated with all pixels which define a display screen are developed in a display memory. Generally, a display memory is implemented by a random access memory (RAM).
An increase in the resolution of displayed images is accompanied by an increase in the time necessary for developing all the video data in the display memory, which is proportional to the square of a resolution. Meanwhile, in order to preserve a predetermined image quality free from flickering, it is desirable that a write access to the display memory be effected within a period of time other than one for reading out video data into the display unit.
Concerning the management of the display memory (video RAM or VRAM), a predominant system is managing it by means of a display controller (CRT controller) independently of a control of a system (host computer). In this kind of system, video data is written in the display memory within those periods of time which are not part of the display of video signals, i.e., during the fly-back and blanking periods as distinguished from effective display periods. Due to such a limitation imposed on the write period, the time necessary for developing one screen of video data increases with the image quality designed for a system. While a write access may be effected by an interrupt during a display period in an attempt to shorten the development time concerned, such will cause the display to flicker resulting in poor display quality.
One of approaches heretofore proposed for overcoming the above-discussed dilemmatic situation is disclosed in Japanese Patent Publication No. 58-36782/1983. The disclosed approach consists in dividing a display period assigned to one pixel into two subcycles to that video data may be read out of a display memory by one of the subcycles and written therein by the other. At the current stage of development, however, such an approach is impractical from the hardware standpoint because in systems which require high resolutions use has to be made of circuit elements capable of behaving at very high speeds.
A bit map system is capable of handling both characters and graphs and, therefore, advantageously applicable to the display of images which include them in mixture. However, the state of the art allows only RAMs whose addressable areas are not greater than the order of 128K bytes to be used as a display memory and, for this reason, has not accomplished a system which can handle various different modes other than the character/graph mixture mode by use of a single VRAM chip. Although various modes may be realized by means of a plurality of VRAM chips, the address compution which covers a plurality of areas at a time would fall in intricacy and consume a longer period of time.